Testability design for sequential circuit with multiple feedback

Abstract

Partial scan testability design method for sequential circuits with multiple feedback is proposed in this paper. The selection of flip-flops is aimed at breaking up the cyclic structure and reducing the sequential depth of the circuit so that test generation can be simplified. Combinational test generation algorithm is used in this method and it can reach ideal fault coverage. Experimental results show that above 90% fault coverage can be obtained by scanning just 20-40% of the flip-flops.