Analysis of High Performance Low Power Full Adder Circuit

Abstract

Over the past few decades, the electronics sector has experienced significant growth. This is all a result of the development of nanotechnology. The advancement of nanotechnology has allowed for the creation of numerous high-speed microelectronic devices that rely on sophisticated computer techniques to maintain their accuracy and effectiveness. With the advent of very large-scale integration (VLSI) designs, the application of integrated circuits (ICs) in high-performance computing systems, telecommunication devices, video and image processing algorithms, control systems and consumer electronics has substantially risen. The most basic element needed for all this processing and computation is the complete adder. A full adder circuit is a crucial part of arithmetic and logic units (ALUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), and a huge variety of different digital systems and circuits. Greater speed, longer battery life, and other qualities are in higher demand as technology advances. Today, creating complete adder circuits that satisfy the expanding demands is one of the biggest challenges facing VLSI architects. Thus, this research survey has covered the prospective technologies that are currently accessible. With the help of this study, the paper intends to provide a comparative analysis of the available architectures and facilitates to come up with a decision on the one that produces the most beneficial outcomes.