An integrated rad-hard test-vehicle for embedded emerging memories

Abstract

An integrated test vehicle architecture for resistive memories is presented. The designed structure, made by two 128kb arrays, allows a systematic characterization of the technology before, during and after the exposure to radiation. For this, after the motivation of the work, the architecture and the design solutions to achieve a high degree of tolerance to radiation effect are discussed; a radiation-hardening-by-design approach is used. A test chip, currently under fabrication, has been implemented using a 250nm CMOS technology.