Hyunwoo Cho, A. Lee, H. Chi, S. Song, Gyeong Su Gwon, Ju Sung Park
{"title":"An ARM7 processor with the Modified Multiplier and the Flip-Flop Based Pipelines","authors":"Hyunwoo Cho, A. Lee, H. Chi, S. Song, Gyeong Su Gwon, Ju Sung Park","doi":"10.1109/IFOST.2006.312249","DOIUrl":null,"url":null,"abstract":"The flip-flop base ARM7 core is designed and fabricated with 0.18 mum CMOS process. The designed processor core can be easily synthesized with the various CMOS libraries because it doesn't have the clock skew and race problem. The conventional ARM7 core has 32times8 multiplier, but we modified the multiplier with 32times16 type to improve the performance of the core. The multiplier is optimized in the point of the operating speed and the gates count. The fabricated chip is tested by the various methods, such as the single instruction test and the instruction combination test, and the application programs. According to the test results, the designed processor carries out the 462 instructions of the processor and the several application algorithms, and the operating at the 98 MHz clock rate.","PeriodicalId":103784,"journal":{"name":"2006 International Forum on Strategic Technology","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Forum on Strategic Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IFOST.2006.312249","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The flip-flop base ARM7 core is designed and fabricated with 0.18 mum CMOS process. The designed processor core can be easily synthesized with the various CMOS libraries because it doesn't have the clock skew and race problem. The conventional ARM7 core has 32times8 multiplier, but we modified the multiplier with 32times16 type to improve the performance of the core. The multiplier is optimized in the point of the operating speed and the gates count. The fabricated chip is tested by the various methods, such as the single instruction test and the instruction combination test, and the application programs. According to the test results, the designed processor carries out the 462 instructions of the processor and the several application algorithms, and the operating at the 98 MHz clock rate.
采用0.18 μ m CMOS工艺设计并制作了基于触发器的ARM7内核。所设计的处理器内核不存在时钟偏差和竞争问题,可以很容易地与各种CMOS库进行合成。传统的ARM7内核是32times8倍频,为了提高内核的性能,我们将其修改为32times16倍频。该乘法器在运行速度和门数方面进行了优化。采用单指令测试和指令组合测试等多种方法对所制备的芯片进行了测试,并编写了应用程序。根据测试结果,所设计的处理器执行处理器的462条指令和几种应用算法,并在98 MHz时钟速率下工作。