A modeling methodology for verifying functionality of a wireless chip

Abstract

This paper describes a modeling methodology for verifying functionality of a mixed signal wireless chip before tape out. Modeling methodologies for mixed signal chips can be distinguished by the way they deal with analog signals. The methodology uses a custom Verilog PLI function to model analog blocks for a digital simulator. The PLI function passes multiple real numbers through one port, in either direction, at any point in time. The key issues the methodology addresses are execution speed, capacity, model portability, and coverage.