An impact of process variation on supply voltage dependence of logic path delay variation

S. Nishizawa, T. Ishihara, H. Onodera
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引用次数: 1

Abstract

Dynamic Voltage and Frequency Scaling (DVFS) technique requires accurate observation of critical path delay for robust operation under aggressive supply voltage scaling. Logic paths contain several types of logic gates and path delay have voltage dependences because different logic gates have different voltage dependences. However, it is not well investigated that how the voltage dependence of the path delay changes induced by process variation. This paper describes the effect of the process variation on the voltage dependence of path delay. Ring Oscillator circuits fabricated in 65-nm CMOS process are used for the evaluation and analysis of the process variation dependence of the voltage delay curves.
动态电压和频率缩放(DVFS)技术需要精确地观察关键路径延迟,以便在积极的电源电压缩放下稳健运行。逻辑路径包含几种类型的逻辑门,由于不同的逻辑门具有不同的电压依赖性,因此路径延迟具有电压依赖性。然而,对于过程变化引起的路径延迟的电压依赖性如何变化的研究还不够深入。本文描述了过程变化对路径延迟电压依赖性的影响。采用65纳米CMOS工艺制作的环形振荡器电路,对电压延迟曲线的工艺变化依赖性进行了评价和分析。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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