Technological solutions for throughput improvement of a Secure Hash Algorithm-256 engine

Abstract

This article describes a set of techniques for improving the performance of an Secure Hash Algorithm 256 (SHA-256) hardware implementation. The proposed solution reduces the latency incurred for updating the intermediate hash values and relies on using combinational tree structures of CSAs interconnected in a Wallace tree manner for multi-operand addition. Furthermore, the paper investigates the throughout improvement provided by a combined implementation of architecture's binary adders with the round functions used by the hash computation process. The proposed acceleration techniques can be adapted to the other members of the SHA-2 family of algorithms. The architecture represents a case study for hardware optimization based on different combinational structures for binary addition and the effect of the carry propagate layer on the overall performance. The synthesis results of the proposed designs are provided as support for the performance analysis presented in this work.