An effective memory addressing scheme for multiprocessor FFT system

Abstract

The memory organization of FFT processors is considered. A new memory addressing scheme is given. The proposed scheme considers the case of using two modules of two-port memory and allows the processing of the butterflies in the form of groups of two. The addressing assignment allows, without any conflict, simultaneous access to the data needed for the two butterflies and to write back the four outputs to the same places. The advantages of this memory-addressing scheme lie in the fact that it reduces the number of the cycles of butterfly calculations of FFT to half and it reduces the delay of address generation to minimum.