{"title":"A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots","authors":"Youchang Kim, Dongjoo Shin, Jinsu Lee, H. Yoo","doi":"10.1109/CoolChips.2016.7503671","DOIUrl":null,"url":null,"abstract":"An ultra-low-power multi-threaded artificial intelligence processor (AIP) is proposed for real-time autonomous navigation of mobile robots. To achieve real-time operation under low power consumption, the proposed AIP adopts 3 key features: 1) an 8-thread tree search processor (TSP) for real-time path planning, 2) a 3-level transposition table cache (TT$) for the reduction of duplicated computations, and 3) an on-chip PVT compensation circuit (PVTC) for energy-efficient operation at near-threshold supply voltage. As a result, it achieves 470,000 state/s search speed and 79 nJ/search energy consumption which are 9.4× and 11× better than the general-purpose CPUs currently used in recent mobile robots. In addition, the AIP is successfully applied to the robots for autonomous navigation without any collision in dynamic environments.","PeriodicalId":273992,"journal":{"name":"2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CoolChips.2016.7503671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An ultra-low-power multi-threaded artificial intelligence processor (AIP) is proposed for real-time autonomous navigation of mobile robots. To achieve real-time operation under low power consumption, the proposed AIP adopts 3 key features: 1) an 8-thread tree search processor (TSP) for real-time path planning, 2) a 3-level transposition table cache (TT$) for the reduction of duplicated computations, and 3) an on-chip PVT compensation circuit (PVTC) for energy-efficient operation at near-threshold supply voltage. As a result, it achieves 470,000 state/s search speed and 79 nJ/search energy consumption which are 9.4× and 11× better than the general-purpose CPUs currently used in recent mobile robots. In addition, the AIP is successfully applied to the robots for autonomous navigation without any collision in dynamic environments.