A 500 V 1A 1-chip inverter IC with a new electric field reduction structure

Abstract

A 500 V 1 A three-phase inverter IC has been developed by using a new electric field reduction structure SRFP (Scroll shaped Resistive-Field-Plate). This HV-IC process is a BiCMOS process with a dielectric isolated (DI) wafer. Si wafer direct bonding (SDB) technique is applied to the DI wafer. Output devices are lateral IGBTs with high-speed collector structures. Without SIPOS, an SRFP has the same field reduction effect and the same electric shield effect as a SIPOS-RFP. In this report, we show that turn off time of IGBT depends on N/sup +/ pattern in the collector and existence of P/sup +/ layer around the DI area. High-speed (280 nsec) and low saturation (2.8 V) voltage IGBTs are realized by using optimization of collector pattern.