Fault Vulnerability Ranking of Transistors in Analog Integrated Circuits using AC Analysis

Abstract

With the increasing complexity of analog circuits in modern Systems on Chip (SOC), and their applications in safety-critical domains, the task of manufacturing fault-free SOCs is becoming more complex. The SOCs need to be designed to be more robust to parametric deviations caused during the fabrication process, any external disturbance or over a period of time due to ageing. In this paper, we propose a novel approach for ranking the transistors in an analog circuit based on their robustness to parametric deviations. We define the concept of fault vulnerability and introduce an associated quantitative measure to develop the ranking. We use time-efficient AC analysis along with a binary search technique for computing this measure. We carry out experiments on some circuits designed in-house and on three of the recently proposed ITC’17 AMS benchmarks. The results indicate that the proposed approach is computationally efficient and quite effective in ranking the transistors in terms of their fault vulnerability.