Three-Level Error Control Coding for Dependable Solid-State Drives

Abstract

Solid-state drive (SSD) has advantages over hard-disk drive (HDD) in terms of power consumption, random access time, and resilience to shock and vibration. Large capacity SSD usually requires high-density multi-level cell flash memory fabricated with deep-submicron process. High-density memory chips, however, are vulnerable to soft errors caused by, for example, fluctuations of gate voltage and charge level in the floating gate. This paper proposes a hierarchical three-level error control coding suitable for the dependable SSD. The proposed coding is capable of correcting multiple random bit errors, as well as of recovering from single chip failures. Evaluation shows that the proposed coding scheme provides strong error correction capability. For example, bit error rate (BER) of the SSD is reduced from 1.08 × 10-4 to 2.44 × 10-19 by using the proposed coding, that is, using two BCH codes with different error correction capabilities for the first and the second levels, and the simple parity-check code for the third level. Extra one spare memory chip in the SSD improves mean time to data loss (MTTDL) from 13 years to 34 years.