Dynamically programmable Reed Solomon processor with embedded Galois Field multiplier

Abstract

This work presents a novel reconfigurable Galois field multiplier embedded in a dynamically reconfigurable processor for real time programmable Reed Solomon (RS) encoder and decoder targeting various communication standards. The fundamental operation in Reed-Solomon encoding and decoding is the multiplication over Galois field (GF). The reconfigurable GF multiplier with single instruction multiple data (SIMD) support is presented here, as an instruction set extension to the processor. The processor supports the RS coding to be programmable for Galois Field (28) with its sixteen primitive polynomials and for all supported data block sizes. Various optimization techniques have been applied in order to enhance the processor throughput. The throughput achieved for RS (204,188) is up to 202 Mbps for the encoder demonstrating a future proof flexible design.