Selective Harmonic Elimination Procedure for Uniform Step Asymmetrical 7-Level CHB Inverter

Abstract

Multilevel converters offer high power capability, low switching losses and low harmonic content in output waveforms. Their main disadvantage is their complexity requiring a great number of power devices and passive components rather than a complex control circuitry. The use of asymmetrical topologies allows to reduce the number of power devices. This paper proposes a three-phase uniform step asymmetrical seven-level cascaded inverter composed by two H-bridges. A simple selective harmonic elimination graphical procedure is introduced to calculate the value of switching angles capable to eliminate fifth and seventh harmonics. The proposed method is compared to multiple optimization methods in order to assess its performance. Simulation results are validated using a small scale laboratory prototype of a three phase seven-level cascaded H-bridge inverter controlled by STM32F407 microcontroller.