{"title":"Fred: an architecture for a self-timed decoupled computer","authors":"W. Richardson, E. Brunvand","doi":"10.1109/ASYNC.1996.494438","DOIUrl":null,"url":null,"abstract":"Decoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred is a self-timed decoupled, pipelined computer architecture based on micropipelines. We present the architecture of Fred, with specific details on a micropipelined implementation that includes support for multiple functional units and out-of-order instruction completion due to the self-timed decoupling.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"1126 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"33","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1996.494438","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 33
Abstract
Decoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred is a self-timed decoupled, pipelined computer architecture based on micropipelines. We present the architecture of Fred, with specific details on a micropipelined implementation that includes support for multiple functional units and out-of-order instruction completion due to the self-timed decoupling.