Numerical simulation of underlap FET device architecture for biosensor applications

Abstract

The paper reports on numerical simulation of underlap field effect transistor (FET) device architecture on silicon-on-insulator (SOI) for a robustness used in biosensors application. By using the Silvaco ATLAS device simulator, the simulation is aimed at elucidating the effect of length of underlap, location of underlap, device etching profiles, and effect of back-gate biasing on the magnitude of drain current (ID). It is shown that the longer underlap and an etched silicon profile introduced higher parasitic resistance, thus decreasing the ID response. The ID response is higher for device with underlap between the gate-drain terminals as compared to gate-source terminals. Positive back-gate bias increases and shifts the current, and reduced the threshold voltage required to turn on the device.