VLSI Implementation of Balanced Binary Tree Decomposition Based 2048-Point FFT/IFFT Processor for Mobile WI-Max

Abstract

Balanced Binary Tree Decomposition(BBTD) based FFT/IFFT processor is proposed for WI-MAX(IEEE 802.16e standard). BBTD algorithm is used for implementation purpose. It uses very few multipliers compared to conventional pipeline based design using Radix-2 Method. Hence this approach gives very good throughput yet highly area efficient design. BBTD algorithm reduces complex multiplier by 33% and twiddle factor by half. Architecture also provides concept of local ROM module, optimized complex multiplier and variable length support from 256-2048 point for FFT/IFFT. Its core size is 3.89 mm^2 with 51.25 μs execution time. Design has been implemented using 0.18 μm CMOS technology standard cell library. The chip size including memories is 3.89 mm^2 with 51.25 μs execution time which satisfies requirement of WI-MAX standard. Total computation is reduced because of less multipliers. This leads to low power architecture. Proposed architecture consumes only 46.57 mW power at 40 MHz which is good for battery operated devices.