Real-time FPGA architecture of extended linear convolution for digital image scaling

Abstract

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The presented architecture is implemented on the Virtex-II FPGA has been successfully designed and implemented. The simulation results demonstrate that the high performance architecture of extended linear interpolation at 104 MHz with 379 LBs is able to process digital image scaling.