A Double-Sided 650 V GaN Power Device Using Flexible Buffers with Low Parasitic Inductance

Abstract

The heat dissipation design and low parasitic inductance are necessary for the packaging of GaN chips. However, due to the planarized structure of GaN chips and the complex finger electrodes on its surface, the GaN devices packaged in the form of double-sided cooling are rarely reported. For enhancing the heat dissipation performance of GaN devices, a new double-sided cooling method is proposed. In this work, we developed a composite buffer, namely copper-wire-spacer (CWS), with anisotropic electrical conductivity. The CWS could cover the GaN chip surface to connect the drain, source and gate pad while avoiding short circuit between them. The GaN chip was packaged between the CWS for pads interconnection and two direct-bond-copper (DBC) for heat dissipation. The proposed method was demonstrated by fabricating single-chip packages of a (650 V, 150 A) GaN HEMT. Silver sintering was used as attachment. The power loop inductance was measured as 3.83 nH. The RDS was measured as 11.2 mΩ.