{"title":"Design of a Wideband Differential RF-Amplifier Using Indigenous 180nm Digital CMOS Technology","authors":"Dibyajyoti Mukherjee, Vinit Kumar, J. Dhar","doi":"10.1109/VLSIDCS47293.2020.9179907","DOIUrl":null,"url":null,"abstract":"In this work, a standard four-metal layer, Indigenous 180nm Digital CMOS Process is chosen for the design of an inductorless wideband differential RF-Amplifier to overcome the limitations of SCL Foundry for designing RF circuits due to non-availabilities of top thick metal, RF models of inductors and interconnects. A capacitor cross-coupled gm - boosting scheme is introduced to improve the wideband gain, input, and output matching while retaining the advantages of the Common Gate (CG) amplifier topology. This design assures wideband response from 650MHz-2.8GHz with the reduced power consumption of 24mW while consuming the chip area of 0.8mm×1.8mm for 4-stage design.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIDCS47293.2020.9179907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, a standard four-metal layer, Indigenous 180nm Digital CMOS Process is chosen for the design of an inductorless wideband differential RF-Amplifier to overcome the limitations of SCL Foundry for designing RF circuits due to non-availabilities of top thick metal, RF models of inductors and interconnects. A capacitor cross-coupled gm - boosting scheme is introduced to improve the wideband gain, input, and output matching while retaining the advantages of the Common Gate (CG) amplifier topology. This design assures wideband response from 650MHz-2.8GHz with the reduced power consumption of 24mW while consuming the chip area of 0.8mm×1.8mm for 4-stage design.