RBM-based hardware accelerator for handwritten digits recognition

Abstract

Automatic recognition of handwritten digits is a well known application area of neural networks. Efficient implementation of neural networks is not a trivial task and various architectures have been proposed for that purpose. This work presents the architecture and implementation of a hardware accelerator for fast recognition of hand-written digits based on Restricted Boltzmann machines. Fixed and floating point arithmetic is used for minimizing the required hardware resources. The proposed architecture results to a processing rate of more than 10 Mimages/sec in a single FPGA board.