{"title":"Efficient FPGA elliptic curve cryptographic processor over GF(2m)","authors":"S. Antão, R. Chaves, L. Sousa","doi":"10.1109/FPT.2008.4762417","DOIUrl":null,"url":null,"abstract":"In this paper a processor that supports elliptic curve cryptographic applications over GF (2m) is proposed. The proposed structure is capable of calculating point multiplication and addition using a single coordinate to contain the point information. This compression allows for a better usage of the bandwidth resources. For the point multiplication procedure, all coordinate pre-calculations are completely avoided. This design was successful prototyped on a reconfigurable device for the field GF (2163). Experimental results suggest that point multiplication can be performed in 144 mus and point affine addition in 1.02 mus. Comparing with the related work, a 5 times speedup is obtained for point addition and multiplication. The presented design offers a well balanced area-time performance when compared with existent elliptic curve point multiplication specific processors.","PeriodicalId":320925,"journal":{"name":"2008 International Conference on Field-Programmable Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Field-Programmable Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPT.2008.4762417","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
In this paper a processor that supports elliptic curve cryptographic applications over GF (2m) is proposed. The proposed structure is capable of calculating point multiplication and addition using a single coordinate to contain the point information. This compression allows for a better usage of the bandwidth resources. For the point multiplication procedure, all coordinate pre-calculations are completely avoided. This design was successful prototyped on a reconfigurable device for the field GF (2163). Experimental results suggest that point multiplication can be performed in 144 mus and point affine addition in 1.02 mus. Comparing with the related work, a 5 times speedup is obtained for point addition and multiplication. The presented design offers a well balanced area-time performance when compared with existent elliptic curve point multiplication specific processors.