Thin relaxed SiGe layers for strained Si CMOS

P. Chen, S.W. Lee, M. Lee, C. Liu, M. Tsai
{"title":"Thin relaxed SiGe layers for strained Si CMOS","authors":"P. Chen, S.W. Lee, M. Lee, C. Liu, M. Tsai","doi":"10.1109/SMTW.2004.1393727","DOIUrl":null,"url":null,"abstract":"High quality, low cost and smooth surface of thin relaxed SiGe layers on new buffers are fabricated. This SiGe nanostructure buffers help thin SiGe uniform layers to relax by introducing some dislocations networks. With these novel Si/Ge buffer, the reduction of thickness of relaxed SiGe uniform layer are from 50 to 75%. The mobility enhancement of the strained Si n-MOSFET deposited on theses relaxed SiGe layer/SiGe buffers are 8 to 40% higher than that of controlled compositional graded SiGe buffers. Such thin relaxed SiGe layers on these new buffers prove to be useful approach to fabricate high quality relaxed epilayers with large lattice mismatch.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMTW.2004.1393727","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

High quality, low cost and smooth surface of thin relaxed SiGe layers on new buffers are fabricated. This SiGe nanostructure buffers help thin SiGe uniform layers to relax by introducing some dislocations networks. With these novel Si/Ge buffer, the reduction of thickness of relaxed SiGe uniform layer are from 50 to 75%. The mobility enhancement of the strained Si n-MOSFET deposited on theses relaxed SiGe layer/SiGe buffers are 8 to 40% higher than that of controlled compositional graded SiGe buffers. Such thin relaxed SiGe layers on these new buffers prove to be useful approach to fabricate high quality relaxed epilayers with large lattice mismatch.
应变Si CMOS的薄松弛SiGe层
在新型缓冲器上制备了高质量、低成本、表面光滑的SiGe薄松弛层。这种SiGe纳米结构缓冲器通过引入一些位错网络来帮助薄的SiGe均匀层放松。使用这种新型的Si/Ge缓冲材料后,松弛SiGe均匀层的厚度减少了50% ~ 75%。在松弛的SiGe层/缓冲层上沉积的应变Si n-MOSFET的迁移率比控制成分梯度的SiGe缓冲层高8 ~ 40%。在这些新的缓冲层上,这种薄的松弛SiGe层被证明是制造具有大晶格错配的高质量松弛脱毛层的有效方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信