Daniel Reiter, Hao Li, H. Knapp, Jonas Kammerer, J. Fritzin, S. Majied, Badou Sene, N. Pohl
{"title":"A 19.5 dBm Power Amplifier with Highly Accurate 8-bit Power Controlling for Automotive Radar Applications in a 28 nm CMOS Technology","authors":"Daniel Reiter, Hao Li, H. Knapp, Jonas Kammerer, J. Fritzin, S. Majied, Badou Sene, N. Pohl","doi":"10.1109/BCICTS45179.2019.8972775","DOIUrl":null,"url":null,"abstract":"A 19.5 dBm power amplifier (PA) with a fine power step-size of 0.5 dB for an output power from 5 dBm to 19.5 dBm is designed and implemented in an advanced CMOS technology. This accurate power controlling is achieved by using an 8-bit digitally controlled current source and this ensures also a stable power controlling over the temperature and supply range with a 29 dB dynamic range. The implemented three-stage PA with a device stacking technique has a maximum small signal gain of 43 dB and delivers a maximum saturated output power of 19.5 dBm at 25 °C and 18.5 dBm at 125 °C. The PA core has an area of 0.053 mm2 and consumes 290 mA including all on-chip biasing circuits from a single 2.1 V power supply. To the best of authors’ knowledge, the achieved maximum output power and also the power step-size are record values in advanced bulk CMOS technologies without power combining.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS45179.2019.8972775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 19.5 dBm power amplifier (PA) with a fine power step-size of 0.5 dB for an output power from 5 dBm to 19.5 dBm is designed and implemented in an advanced CMOS technology. This accurate power controlling is achieved by using an 8-bit digitally controlled current source and this ensures also a stable power controlling over the temperature and supply range with a 29 dB dynamic range. The implemented three-stage PA with a device stacking technique has a maximum small signal gain of 43 dB and delivers a maximum saturated output power of 19.5 dBm at 25 °C and 18.5 dBm at 125 °C. The PA core has an area of 0.053 mm2 and consumes 290 mA including all on-chip biasing circuits from a single 2.1 V power supply. To the best of authors’ knowledge, the achieved maximum output power and also the power step-size are record values in advanced bulk CMOS technologies without power combining.