Limiting oxide failure mode versus oxide thickness. Some insights for deep-submicron technologies

Abstract

This paper focuses on the different aspects related to the gate oxide reliability for oxide thicknesses ranging between 7 and 2.5 nm in order to get some insights on the failure modes which will dominantly limit the future technologies' dielectric reliability. First, the SILC bell-shaped behavior with the oxide thickness presages that the SILC will not be a dielectric reliability limitation for the future CMOS technologies. Second, the impact of the larger spread of the intrinsic breakdown distribution on the oxide lifetime is underlined. Third, the quasi-breakdown occurrence is characterized and a methodology is proposed in order to statistically analyze quasi-breakdown phenomenon. Finally, the question of the oxide limiting failure mode is developed: for oxide thicknesses ranging between 5 and 3 nm, quasi-breakdown phenomenon appears to be the most limiting failure mode; on the contrary, for 2.5 nm oxide and probably thinner, the breakdown event occurs before the quasi-breakdown one at nominal conditions.