Shang-Chun Chen, P. Tzeng, Yu-Chen Hsm, Chung-Chih Wang, Po-Chih Chang, Jui-Chm Chen, Yiu-Hsiang Chang, Tsuen-Sung Chen, T. Hsu, Hsiang-Hung Chang, C. Zhan, Chia-Hsin Lee, Yung-Fa Chou, D. Kwai, T. Ku, Pei-Hua Wang, W. Lo
{"title":"Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration","authors":"Shang-Chun Chen, P. Tzeng, Yu-Chen Hsm, Chung-Chih Wang, Po-Chih Chang, Jui-Chm Chen, Yiu-Hsiang Chang, Tsuen-Sung Chen, T. Hsu, Hsiang-Hung Chang, C. Zhan, Chia-Hsin Lee, Yung-Fa Chou, D. Kwai, T. Ku, Pei-Hua Wang, W. Lo","doi":"10.1109/VLSI-TSA.2016.7480522","DOIUrl":null,"url":null,"abstract":"Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2016.7480522","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.