Test compaction in a parallel access scan environment

Abstract

In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-in/out operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.