Impedance renormalization in CMOS-based single-element electronic de-embedding

Abstract

In this work, an impedance renormalization technique dedicated for single-element de-embedding algorithm is proposed. By performing impedance modulation using CMOS transistors, reflection measurements with both ideal shorts and opens are generated from the measured two-port S-parameters. Such measurements with known terminations are further utilized for finding the solution to the test fixture and the characteristic impedance of the on-chip transmission line. As a single structure is sufficient, considerable savings in silicon area and improved accuracy due to reduced number of probing is achievable. Experimental results up to 65 GHz have validated the proposed single-element approach.