Design and Simulation of an Incremental Sigma-Delta Converter for Improving the Noise Floor Level of CMOS Image Sensors

Abstract

Flicker and thermal noise are the two most important noise contributors that limit the low-light noise performance on CMOS Image Sensors. There are several techniques to mitigate each and enhance the noise floor level of CMOS imagers, such as readout bandwidth limitation, Correlated Double Sampling, Correlated Multiple Sampling, among other techniques. The limiting factor in achieving low output noise at low-light levels is known to be due to flicker noise, since the thermal noise contribution is nowadays well controlled by proper circuitry design. This paper presents a mean to further decrease output noise due to flicker noise by means of reducing time for the correlated samples, as well as to further reduce thermal noise contribution through the usage of a high order Incremental Sigma-Delta converter. In addition, the paper presents a small study on how to approach the design of such ADC type, namely finding the ADC modulator coefficients for a stable operation. The proposed analog-to-digital converter is verified by means of behavioral and extensive transistor-level simulations, done with Cadence Virtuoso 6.15 and using models from Image Sensor Tower Jazz 0.18um Process Development Kit, TS18IS module.