A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM

Abstract

On-chip power grid design is a major challenge in submicron technologies. High peak current coupled with inductive reactance of supply mesh results in power integrity issue results in ringing. This supply noise reduces the available differential voltage for sensing and results in read failure in Read only memory (ROM). Controlling the noise by using large decoupling capacitor is area consuming. Proposed scheme uses a noise tolerant reference generation. Scheme reduces the coupling effect of noise on differential nodes at Sense Amplifier. This is done by decoupling the differential nodes from power supply noise using highly capacitive shared reference lines. Thus, the impact of supply noise on differential voltage is reduced by ~90%. Scheme results in improvement in speed and power by 20% and 5% respectively with no area loss. We achieved 50MHz operating frequency with 8T-NAND High VT (HVT) ROM for 8192×128 (i.e. 8K words and 128 bits) instance.