Fpga implementation of optimized sorting network algorithm for median filters

Abstract

Median filters commonly used in image processing applications for the removal of impulse noise. Over the years so many median filters such as are separable median filters, recursive median filters, weighted median filters, max-median filters and multistage median filters were developed. Sorting networks are of major concern for real time hardware implementation of filters. Sorting is a computationally expensive operation as it consumes large area, speed and power. In this work, effective VLSI hardware implementation has been proposed as an economical solution for sorting networks in terms of area speed, power. The proposed work uses a new carry select comparator in the first section which uses compare and swap functions and its pipelined version in second section, thereby reducing the complexity of the sorting networks. The proposed Carry select comparator uses one half subractor, 7 full subractor, few multiplexers and inverters. The proposed algorithm will definitely overcome the problems by performing median calculation within 7 clock cycles. This work had been compared with existing carry select logic and its pipelined version occupies which occupies less area, consumes low power and works at 113.225 MHz for the device Devices XC2s100e–7tq144.