Power-aware clock routing in 7nm designs

Abstract

The latest advancement in nanotechnology across a different range of industries, and the increased microelectronics market demand for high-performance, high complexity, and low power System on Chips (SoCs) have pushed the Electronic Design Automation (EDA) vendors to explore and to innovate in all stages and aspects of the design development cycle. Nowadays, some IC foundries have enabled the 7nm node for mass production and have seduced many industries to target this technology for their future devices. This market trend has brought many challenges for EDA vendors and physical design and verification specialists since they need to account for many new physical constraints and design rules in order to meet the foundry requirements. On the other side, 7nm node came with new opportunities and advantages that did not exist in earlier design nodes. In this paper, we will use one of these benefits while exploring the low power clock routing problem to achieve better clock power reduction without impacting the circuit timing or area. Our approach takes advantage of the big resistivity differences between SADP and Non-SADP layer to reduce the overall clock parasitic load to be balanced by the clock driver, which will reduce the number of inverters and buffers needed to drive all clock leaf cells, and by consequence, results in an important clock power reduction. By applying our new clock routing approach on a real 7nm testcase using Nitro-SoC place and route tool of Mentor Graphics, we achieved an improvement of 14.7% in clock nets power, 4% in clock cells power, a timing improvement of 1.7% in TNS, and 9.8% in WNS, with better utilization and less total wirelength.