Design and optimization of a 250nm SOI LDMOSFET

G. Camuso, F. Udrea, E. Napoli, X. Luo
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Abstract

This work is aimed at optimising the static performance of a high voltage SOI LDMOSFET. Starting with a conventional LDMOSFET, 2D and 3D numerical simulation models, able to accurately match datasheet values, have been developed. Moving from the original device, several design techniques have been investigated with the target of improving the breakdown voltage and the ON-state resistance. The considered design techniques are based on the modification of the doping profile of the drift region and the Superjunction design technique. The paper shows that a single step doping within the drift region is the best design choice for the considered device and is found to give a 24% improvement in the breakdown voltage and a 17% reduction of the ON-state resistance.
250nm SOI LDMOSFET的设计与优化
本工作旨在优化高压SOI LDMOSFET的静态性能。从传统的LDMOSFET开始,已经开发出能够准确匹配数据表值的2D和3D数值模拟模型。从原始器件出发,研究了几种设计技术,目标是提高击穿电压和导通状态电阻。所考虑的设计技术是基于漂移区掺杂轮廓的修改和超结设计技术。本文表明,对于所考虑的器件,在漂移区域内单步掺杂是最佳设计选择,并且发现击穿电压提高24%,导通状态电阻降低17%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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