Automated signal selection maximizing circuit coverage for efficient debug

Abstract

As the complexity of chip increases, the importance of post silicon verification is escalated. Trace buffer is a commonly used hardware architecture to achieve an efficient debug process. It is advantageous since it is able to store internal values which are captured during system operation at-speed. However, it cannot store a vast number of signals due to its limited storage. Therefore, it is very important to select appropriate internal signals for efficient debug. In this paper, we propose a new signal selection scheme to detect errors as close as its occurrence cycle.