C. Gimeno, E. Guerrero, C. Sánchez-Azqueta, C. Aldea, S. Celma
{"title":"A 1-V CMOS double loop continuous-time adaptive equalizer for short-haul optical networks","authors":"C. Gimeno, E. Guerrero, C. Sánchez-Azqueta, C. Aldea, S. Celma","doi":"10.1109/SSD.2014.6808861","DOIUrl":null,"url":null,"abstract":"This paper presents a low-voltage CMOS continuous-time adaptive equalizer for short-haul gigabit optical communications. It was designed to compensate the attenuation of a 1.25 Gb/s signal with a simple NRZ modulation, transmitted through a 50-m length 1-mm core step-index plastic optical fiber (SI-POF). The structure includes two adaptation loops to compensate the possible variations in level and spectrum of the input signal. The proposed system was designed in a cost-effective 0.18-μm CMOS process. The system is fed with 1 V and has a total power consumption of 29.3 mW.","PeriodicalId":168063,"journal":{"name":"2014 IEEE 11th International Multi-Conference on Systems, Signals & Devices (SSD14)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 11th International Multi-Conference on Systems, Signals & Devices (SSD14)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSD.2014.6808861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a low-voltage CMOS continuous-time adaptive equalizer for short-haul gigabit optical communications. It was designed to compensate the attenuation of a 1.25 Gb/s signal with a simple NRZ modulation, transmitted through a 50-m length 1-mm core step-index plastic optical fiber (SI-POF). The structure includes two adaptation loops to compensate the possible variations in level and spectrum of the input signal. The proposed system was designed in a cost-effective 0.18-μm CMOS process. The system is fed with 1 V and has a total power consumption of 29.3 mW.