Integer-N digital PLL using ADC-based phase detector

Abstract

Phase-to-digital converter (PDC) is a critical building block in digital phase-locked loops (DPLL). To improve its phase noise performance, an integer-N DPLL that employs an analog-to-digital converter (ADC) to digitize the phase error is presented. Compared to the conventional time-to-digital converter (TDC), the proposed ADC-based PDC with the same number of bits can be shown to reduce the quantization noise contribution to the DPLL output jitter variance by more than an order of magnitude. Design examples are presented to verify the functionality and performance of the proposed approach.