{"title":"Design of HWSI multichip modules for quick prototyping and manufacturing","authors":"Y. Lee","doi":"10.1109/ECTC.1990.122247","DOIUrl":null,"url":null,"abstract":"The constraints imposed by the semicustom approach on multichip module designs are studied using a design case that interconnects a 144-input/output (I/O) microprocessor and four memory chips. The results show that semicustom hybrid wafer-scale-integration (HWSI) has enough real estate for complex designs even with the constraints on interconnection: a low inductance level (<0.2 nH) per power/ground (P/G) connection, even with an additional connection from a solder bump to a near thermal via; and alternative thermal management schemes to replace the ineffective thermal paths using solder bumps and thermal vias. These schemes use a custom-designed standard substrate for high-power chips, an alternative thermal path having enhanced gap conduction, or a compact immersion cooling design.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"205 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"40th Conference Proceedings on Electronic Components and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.1990.122247","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The constraints imposed by the semicustom approach on multichip module designs are studied using a design case that interconnects a 144-input/output (I/O) microprocessor and four memory chips. The results show that semicustom hybrid wafer-scale-integration (HWSI) has enough real estate for complex designs even with the constraints on interconnection: a low inductance level (<0.2 nH) per power/ground (P/G) connection, even with an additional connection from a solder bump to a near thermal via; and alternative thermal management schemes to replace the ineffective thermal paths using solder bumps and thermal vias. These schemes use a custom-designed standard substrate for high-power chips, an alternative thermal path having enhanced gap conduction, or a compact immersion cooling design.<>