Multi-signature Analysis For Interconnect Test

Abstract

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of a little diagnostic resolution. The second step (which is made only in the case of the detection of faults in the first step) is the localization step by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures. The use of two signatures eliminates aliasing of static faults while adding the third signature enables dependable identification of such faults. The theory given in the paper is partially illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable