{"title":"A 1V low-power low-noise biopotential amplifier based on flipped voltage follower","authors":"Tamer Farouk, M. Elkhatib, M. Dessouky","doi":"10.1109/ICECS.2015.7440373","DOIUrl":null,"url":null,"abstract":"This paper presents a low-voltage low-power low-noise amplifier suitable for neural recording applications. Based on the flipped voltage follower (FVF) topology, the amplifier is able to operate under a 1 V supply by alleviating the tradeoff between the noise and the voltage headroom. A gm-cell was built using FVF, its effective transconductance is not a function of the bias current, so the noise contribution of the output transistors can be decreased without increasing the bias current. This amplifier is designed and simulated in a 130 nm CMOS process. The amplifier consumes 2.2 μW from 1 V supply voltage. The input referred noise is 3.7 μVrms. The amplifier has a BW from 25 Hz to 9.9 kHz.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2015.7440373","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a low-voltage low-power low-noise amplifier suitable for neural recording applications. Based on the flipped voltage follower (FVF) topology, the amplifier is able to operate under a 1 V supply by alleviating the tradeoff between the noise and the voltage headroom. A gm-cell was built using FVF, its effective transconductance is not a function of the bias current, so the noise contribution of the output transistors can be decreased without increasing the bias current. This amplifier is designed and simulated in a 130 nm CMOS process. The amplifier consumes 2.2 μW from 1 V supply voltage. The input referred noise is 3.7 μVrms. The amplifier has a BW from 25 Hz to 9.9 kHz.