The novel Chinese abacus adder

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI:10.1109/VDAT.2007.372759

Zi-Yi Zhao, Chien-Hung Lin, Yu-Zhi Xie, Yen-Ju Chen, Yi-Jie Lin, Shu-Chung Yi

引用次数: 9

Abstract

A novel Chinese abacus adder is presented in this paper. The simulation results of 8-bit adders are compared with those of CLA (carry look-ahead) adder and RCA (ripple carry adder) by all input patterns. The delay of the 8-bit abacus adder is 22%, and 14% less than those of CLA adders for 0.35mum and 0.18mum technologies, respectively. The power consumption of the abacus adders are 30% and 60% less than those of CLA adders for 0.35mum, and 0.18mum technologies, respectively. The delay of the 32-bit abacus adder is 17%, and 12% less than those of CLA adder for 0.35mum, and 0.18mum technologies, respectively.

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新颖的中国算盘加法器

本文提出了一种新的中国算盘加法器。在所有输入模式下，将8位加法器的仿真结果与超前进位加法器(CLA)和纹波进位加法器(RCA)的仿真结果进行比较。8位算盘加法器的延迟分别比0.35 μ m和0.18 μ m技术的CLA加法器低22%和14%。在0.35 μ m和0.18 μ m技术下，珠算加法器的功耗分别比CLA加法器低30%和60%。32位算盘加法器在0.35和0.18技术下的延迟分别比CLA加法器低17%和12%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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