A low power DSP core for an embedded MP3 decoder

Abstract

A low power 32-bit 20 MIPS DSP core designed for MPEG1 Audio Layer III (MP3) decoder is proposed. It has an architecture designed specifically for MP3 decoding algorithm implementation. The authors used the instruction level clock gating technique to achieve lower power for portable applications besides other effective dynamic power management schemes. A 0.25 /spl mu/m, 2.5 V CMOS process was used.