Analysis of die-to-die vertical crosstalk between Clock-tree and Voltage Controlled Oscillator in 3-D IC

Abstract

Vertical crosstalk problem between digital and analog circuit components in 3-D IC can severely degrade the 3-D IC system performance. In this paper, we analyze the performance degradation mechanism of 3-D IC that induced by vertical crosstalk between Clock-tree and Voltage Controlled Oscillator (VCO). The 3-D IC test chip which contains Clock-tree and spiral inductor of VCO is fabricated. Lumped component vertical crosstalk model is proposed and it is validated with measurement result. Using validated vertical crosstalk model and spice circuit of VCO, circuit level simulation is performed. Performance degradation mechanism of VCO in 3-D IC is analyzed by separation of noise coupling path approach, and the main mechanism is revealed as high frequency multiplicative noise on signal path.