Advances on III-V on Silicon DBR and DFB Lasers for WDM Optical Interconnects and Associated Heterogeneous Integration 200mm-Wafer-Scale Technology

S. Menezo, H. Duprez, A. Descos, D. Bordel, L. Sanchez, P. Brianceau, L. Fulbert, V. Carron, B. Ben Bakir
{"title":"Advances on III-V on Silicon DBR and DFB Lasers for WDM Optical Interconnects and Associated Heterogeneous Integration 200mm-Wafer-Scale Technology","authors":"S. Menezo, H. Duprez, A. Descos, D. Bordel, L. Sanchez, P. Brianceau, L. Fulbert, V. Carron, B. Ben Bakir","doi":"10.1109/CSICS.2014.6978538","DOIUrl":null,"url":null,"abstract":"In the absence of practically efficient lasers achievable directly in Silicon or other group IV materials, Si-photonic transmitter sources must be made by \"Hybrid integration\" of III-V chips or \"Heterogeneous integration\" with III-V gain materials. \"Hybrid integration\" technologies consist in integrating processed (and finished) chips in a photonic microsystem. One commercial solution (from LUXTERA) makes use of a InP-bulk- processed laser-chip [3]. The laser chip is attached to the PIC, and its light is coupled into the PIC- waveguide by means of a lens, followed by an optical isolator, and a mirror for directing the light to a surface grating coupler in the Si-PIC. Other approaches (from KOTURA/ORACLE) consist in but-coupling a III-V- semiconductor reflective-SOA to the PIC-3μm- thick-Si-waveguide that comprises a Bragg-mirror for defining the laser cavity [4]. This forms an external-cavity DBR laser, with reported Waveguide-Coupled Wall-Plug-Efficiencies (WC-WPE) for the uncooled lasers of up to 9.5% at powers of 6 mW. In spite of the good demonstrated performances, this solution requires an accurate alignment between the R-SOA and the Si-PIC, limiting the capability for a low cost fabrication. As a more economical route that we opted for, \"Heterogeneous integration\" technologies were proposed [5], [6] together with new laser architectures. An InP-wafer having the III-V-gain- layers grown on top is bonded with loose alignment requirements (~50μm), the III-V gain-layers facing down to the bottom Silicon-On- Insulator (SOI) wafer on which silicon waveguides are pre- processed. In a more economical route, the InP-substrate having the laser III-V-gain- layers on top is first diced, and the dies are bonded where needed. Then the InP-substrate is removed, and the laser process is continued on the remaining III-V gain epi-layers, in a regular wafer level process flow. Putting the expensive III-V-gain material only where needed saves on cost. In addition to lower cost, photonic integration promises improved reliability and performances and reduced footprints over discrete components systems. This paper will report on our recent advances on both, 1) the developed III-V on Silicon lasers (DBR and DFB types) built up from heterogeneous integration, and, 2) the development of the integration technology for processing the lasers on 200mm-wafers, with industrial CMOS tools at very low cost.","PeriodicalId":309722,"journal":{"name":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2014.6978538","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

In the absence of practically efficient lasers achievable directly in Silicon or other group IV materials, Si-photonic transmitter sources must be made by "Hybrid integration" of III-V chips or "Heterogeneous integration" with III-V gain materials. "Hybrid integration" technologies consist in integrating processed (and finished) chips in a photonic microsystem. One commercial solution (from LUXTERA) makes use of a InP-bulk- processed laser-chip [3]. The laser chip is attached to the PIC, and its light is coupled into the PIC- waveguide by means of a lens, followed by an optical isolator, and a mirror for directing the light to a surface grating coupler in the Si-PIC. Other approaches (from KOTURA/ORACLE) consist in but-coupling a III-V- semiconductor reflective-SOA to the PIC-3μm- thick-Si-waveguide that comprises a Bragg-mirror for defining the laser cavity [4]. This forms an external-cavity DBR laser, with reported Waveguide-Coupled Wall-Plug-Efficiencies (WC-WPE) for the uncooled lasers of up to 9.5% at powers of 6 mW. In spite of the good demonstrated performances, this solution requires an accurate alignment between the R-SOA and the Si-PIC, limiting the capability for a low cost fabrication. As a more economical route that we opted for, "Heterogeneous integration" technologies were proposed [5], [6] together with new laser architectures. An InP-wafer having the III-V-gain- layers grown on top is bonded with loose alignment requirements (~50μm), the III-V gain-layers facing down to the bottom Silicon-On- Insulator (SOI) wafer on which silicon waveguides are pre- processed. In a more economical route, the InP-substrate having the laser III-V-gain- layers on top is first diced, and the dies are bonded where needed. Then the InP-substrate is removed, and the laser process is continued on the remaining III-V gain epi-layers, in a regular wafer level process flow. Putting the expensive III-V-gain material only where needed saves on cost. In addition to lower cost, photonic integration promises improved reliability and performances and reduced footprints over discrete components systems. This paper will report on our recent advances on both, 1) the developed III-V on Silicon lasers (DBR and DFB types) built up from heterogeneous integration, and, 2) the development of the integration technology for processing the lasers on 200mm-wafers, with industrial CMOS tools at very low cost.
用于WDM光互连及相关非均匀集成200mm晶圆级技术的硅DBR和DFB激光器III-V研究进展
在硅或其他IV族材料中无法直接实现实际有效的激光器的情况下,硅光子发射源必须通过III-V类芯片的“混合集成”或与III-V类增益材料的“非均质集成”来制造。“混合集成”技术包括将加工(和成品)芯片集成到光子微系统中。一种商业解决方案(来自LUXTERA)利用了inp批量加工的激光芯片[3]。激光芯片附着在PIC上,其光通过透镜耦合到PIC-波导中,随后是光隔离器和反射镜,用于将光定向到Si-PIC中的表面光栅耦合器。其他方法(来自KOTURA/ORACLE)包括将III-V-半导体反射soa耦合到PIC-3μm厚的si波导,该波导包含用于定义激光腔的布拉格反射镜[4]。这形成了一种外腔DBR激光器,据报道,在功率为6 mW的非冷却激光器中,波导耦合壁塞效率(WC-WPE)高达9.5%。尽管具有良好的性能,但该解决方案需要在R-SOA和Si-PIC之间进行精确校准,从而限制了低成本制造的能力。作为我们选择的更经济的途径,我们提出了“异构集成”技术[5],[6]以及新的激光架构。具有III-V增益层生长在顶部的inp晶圆与松散对准要求(~50μm)结合,III-V增益层面向底部硅绝缘体(SOI)晶圆,硅波导在其上进行预处理。在一种更经济的方法中,首先将具有激光iii - v增益层的inp衬底切割,并在需要的地方粘合模具。然后去除inp衬底,在剩余的III-V增益外延层上继续激光工艺,以常规晶圆级工艺流程进行。将昂贵的iii - v增益材料只放在需要的地方可以节省成本。除了降低成本外,光子集成还有望提高可靠性和性能,并减少离散元件系统的占地面积。本文将报告我们在以下两方面的最新进展:1)基于异质集成的III-V硅激光器(DBR和DFB类型)的开发,以及2)利用工业CMOS工具以非常低的成本在200mm晶圆上加工激光器的集成技术的发展。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信