Evaluation and integrated diagnostic of high speed narrow band power-line chipset

G. Bmiller
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引用次数: 7

Abstract

The narrow band power-line communication market is very interesting for utility services, automation, building facilities and so on. The available bandwidth is limited and data rates of several Mbps will not be possible. But the frequency range below 500 kHz has a lot of advantages. The EMC problems are very small compared with BPLC [Harald Dalichau, 2001]. The situation for regulation with CENELEC and FCC is much better. Independent use of the same medium and interoperability with BPLC is possible. The attenuation of the cables and the branches are much lower [Manfred Zimmermann] and it is possible to reach for example distances of 60 km (offshore umbilical cord) without any repeater. This is very important, if we look for reliable systems with a complete coverage of an area and real time requirements. Too much repeaters increase the costs, complicate the network management, reduce the reliability and limit the real time possibilities. Due to it IAd decided to produce two chip sets for this kind of market. The first concept for these chipsets was already presented on the 5th ISPLC in Malmo. Meanwhile, the design of the chipsets is ready, emulation boards with engineering samples of the analog ASIC and a complete design of the digital chip in an FPGA are built, software tools for diagnostic and test are implemented and all is in use for evaluation and first field trials. During the design we spent a lot of effort into the integration of measurement tools to analyse disturbers and characterise the transmission channel without any external measurement equipment. As in the past IAd is the expert for difficult power-line channels and therefore, we define our goal for the development as: 'if it is possible to communicate over a channel, our system has to do it' and this is equal to 'there never should be a system, which is able to communicate, but our one not.' Only if we deliver the best quality we get the confidence of our customer. If problems happen in the field we have to present the way, how to analyse the source of the problem and deliver solutions without additional costs. To reach this goal in the field, the integrated diagnostic is an important part.
高速窄带电力线芯片组的评估与综合诊断
窄带电力线通信市场对公用事业服务、自动化、建筑设施等非常有吸引力。可用带宽有限,不可能达到几Mbps的数据速率。但是低于500千赫的频率范围有很多优点。与BPLC相比,EMC问题非常小[Harald Dalichau, 2001]。与CENELEC和FCC的监管情况要好得多。可以独立使用相同的介质并与BPLC互操作。电缆和分支的衰减要低得多[Manfred Zimmermann],并且可以在没有任何中继器的情况下达到例如60公里的距离(海上脐带)。这是非常重要的,如果我们寻找可靠的系统,完全覆盖一个地区和实时需求。过多的中继器增加了成本,使网络管理复杂化,降低了可靠性,限制了实时性的可能性。因此,我决定为这类市场生产两种芯片组。这些芯片组的第一个概念已经在马尔默举行的第5届ISPLC上提出。同时,芯片组的设计已经准备好,模拟ASIC的工程样本仿真板和FPGA中数字芯片的完整设计已经构建,诊断和测试软件工具已经实现,所有这些都用于评估和首次现场试验。在设计过程中,我们花了很多精力集成测量工具来分析干扰器并表征传输通道,而无需任何外部测量设备。在过去,IAd是困难电力线信道的专家,因此,我们将开发目标定义为:“如果有可能通过信道进行通信,我们的系统必须做到这一点”,这等于“不应该有一个系统能够通信,但我们的系统不能。”只有我们提供最好的质量,我们才能得到客户的信任。如果问题发生在现场,我们必须提出方法,如何分析问题的根源,并在不增加成本的情况下提供解决方案。综合诊断是实现这一目标的重要组成部分。
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