Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths

Abstract

In-situ delay monitoring is an advanced technique to monitor the robustness of digital circuits. Conventionally, in-situ delay monitors are inserted at the end-points of timing paths. To reduce the number of monitors and to increase their observability, intermediate points have been considered. In sharp contrast to these works, we propose a low overhead technique where the insertion points are selected along the timing paths such that timing violations can be predicted without false negative detections. With our approach, the number of required monitors is reduced by up to 11X compared to end-point insertion techniques. The observability to delay degradation is 8X better with our approach, compared to techniques with straight monitor placement at intermediate points.