FPGA implementation of wavelet filters for power system harmonics estimation

Abstract

In hardware implementation of any signal processing algorithm, computational time and hardware resources are crucial issues. This paper presents design and implementation of a new architecture of wavelet filter for power system harmonics estimation using discrete wavelet packet transform (DWPT). Usually, DWPT provides coefficients as the output, however, the proposed architecture also includes provision for providing rms values directly. The proposed method reduces computational requirements and save memory resources. Xilinx system generator, a higher abstraction level tool, has been used to simulate and implement the proposed scheme on the Xilinx Artix-7 FPGA AC-701 board. Performance of the proposed architecture has been validated and compared through hardware co-simulation with variety of synthetic and experimental signals.