TDDB chip reliability in copper interconnects

Abstract

Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.