The analyze and design of low FPN double delta sampling circuit for CMOS image sensor

Abstract

This paper presents an improved double delta sampling (DDS) circuit and the architecture and readout sequence are introduced in detail. Meanwhile, a new method to evaluate the Fixed Pattern Noise (FPN) cancellation for readout circuit before fabricated is proposed. Thus, we can evaluate DDS or other readout circuit in another view. Compared with the conventional DDS circuit, the new architecture is better overall performance. Simulation results indicate the improved DDS circuit can achieve SNR (Signal Noise Ratio) of 72.12 dB and SFDR (Spurious Free Dynamic Range) of 73.39 dB with a sampling frequency of 10MHz. Through the proposed method, we calculated that the level of FPN cancellation achieves 11.6 bits on average and 15.2 bits on maximum.