FPGA Implementation of Visual Noise Optimized Online Steady-State Motion Visual Evoked Potential BCI System*

Abstract

In order to improve the practicability of brain computer interface (BCI) system based on steady-state visual evoked potential (SSVEP), it is necessary to design BCI equipment with portability and low-cost. According to the principle of stochastic resonance (SR), the recognition accuracy of visual evoked potential could be improved by full-screen visual noise. Based on the above requirements, this paper proposed the usage of field programmable gate array (FPGA) to control stimulator through high definition multimedia interface (HDMI) for the display of steady-state motion visual evoked potential (SSMVEP) paradigm. By adding spatially localized visual noise to the motion-reversal checkerboard paradigm, the recognition accuracy is improved. According to the experimental results under different noise levels, the average recognition accuracies calculated with occipital electrodes O1, Oz, O2, PO3, POz and PO4 are 77.2%, 87.5%, and 85.2% corresponding to noise standard deviations values of 0, 24, and 40, respectively. In order to analyze the SR effect on the recognition accuracy with utilization of spatially localized visual noise, statistical analyses on the recognition accuracies under different noise intensities and different channel combinations are carried out. Results showed that the spatially localized visual noise could significantly improve the recognition accuracy and the stability of the proposed FPGA based online SSMVEP BCI system.