Power Rail Noise Minimization during Mode Transition in a Dual Core Processor

Abstract

Optimum Power gating sleep transistor design and implementation are critical to a successful low-power design. The large magnitude of supply and ground bounces, which arise from power mode transitions in large power gating structures results in wrong functioning of the circuit. We propose a novel power gating technique showing the trade-off between wake-up time and supply noise. This technique is simulated for a dual-core processor for 32nm CMOS technology and the supply rail noise is reduced to 1.35 mV.